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Switch mode regulators
6 V7 r2 K% U7 F2 `, h8 MQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators$ c) K! i$ n! u L/ F( }+ @
receive power from VBAT or VCHG under application software control.7 P6 {3 B4 `7 o: O E) |6 n( g% K, |
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040
6 \0 j- j6 D& I0 r5 R7 v: n9 xVFBGA and the flash memory. The System SMPS can supply power to external components.; X; |8 F8 a9 G' u
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
+ P- j0 I' f8 Tbetween 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
- B" o' c1 Z. S4 r& ?5 S5 G/ sThe SMPS both have three operating modes:
, a8 }& k4 o9 [2 e. w# }5 n■ Normal (PWM)+ d* F/ D8 f7 x8 Q! r9 h6 D
■ Two low-power modes with reduced current capability:
& F" Z0 z$ `- D/ y□ PFM
' g2 l( w: ^1 r) G' p□ ULP; v @9 M/ G" `% U- _4 N
Normally the system auto switches, but this is optionally disabled.6 l3 B! I/ {3 ~2 Y6 S7 L
The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
0 n: z1 j r, U' n* Z% {For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-
8 p# C' z0 o. M# o& V: @1 |; ?CH285-1).- W5 l" O& T g% N8 a2 o
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
% n; }9 r! `0 Pa 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.$ G: q( @, Z4 n d W% b0 s
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
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