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軟件是ISE14.7，芯片是XC3S50
$ h, s y- D4 v( s S# RChipScope生成cdc文件的時(shí)候都沒(méi)有問(wèn)題
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' a Y( v; A# w; N8 k5 r/ F/ n& m3 k但是在加載bit文件的時(shí)候出現(xiàn)如下錯(cuò)誤：9 c* G7 P) G) `: Q* x- N: Y
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COMMAND: open_cable
J3 y& A n5 s( N a/ j; N9 E" w, cINFO: Started ChipScope host (localhost:50001)% \7 W6 ]5 B- ]& m
INFO: Successfully opened connection to server: localhost:50001 (localhost/127.0.0.1)6 Y# y w* ] ]) ~$ G" }
INFO: Trying to open Xilinx Platform USB Cable on port USB28 n0 n( p7 B% a0 o- g
INFO: Successfully opened Xilinx Platform USB Cable
$ A1 c( i( J( ^INFO: Cable: Platform Cable USB II, Port: USB21, Speed: 3 MHz" M- C7 w0 Z5 h. l" Q! Q
INFO: Found 0 Core Units in the JTAG device Chain.
3 C( ~, M4 S' Y; O' bINFO: If cores were expected to be found, see Answer Record 19337.1 ]) ]. k7 C0 i
COMMAND: configure 1 "D:\FPGA\Timing_chipscope\main.bit" 0 import_inserter_cdc "D:\FPGA\Timing_chipscope\" "chipscopewave.cdc" doAuto9 W4 p. k# k/ h
ERROR: Configuration failed.8 z5 r/ z1 o1 m
INFO: DEV:1 MyDevice1 (XC3S50) is not configured
! r2 D; J* U. X- b& Z9 QCOMMAND: import_inserter_cdc "D:\FPGA\Timing_chipscope\" "chipscopewave.cdc" 1 DoAuto
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ps：下載線是正常的，試過(guò)了沒(méi)問(wèn)題' l1 \3 J; a: [! [4 L
請(qǐng)問(wèn)是什么原因？) p' G- y7 \( d
該如何解決？
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