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本帖最后由 深圳-綠皮 于 2013-11-22 10:14 編輯 - o# f- a4 S$ j$ r* u
8 k0 H8 k6 f8 t1 z% r- }DATE: 11-15-2013 HOTFIX VERSION: 019& m8 S- @) Y5 d8 m! r
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( K" }! T1 W1 X1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 31 x, Z/ q3 U. N; _
1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly* q* p0 ?3 S1 [
1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.
: o) F" @% B- B' Z- v! h7 c1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings
$ x- B( F `; V* K1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.
& B- c* C( X% Q6 {- p/ t( f6 M3 i1196704 allegro_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected2 i- m5 c0 Z0 x
1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product, ], v5 m: ?) K" J8 s% o
1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.1 X4 D. w3 S, w2 G8 O5 w
1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path
" x% y$ V' a3 u7 N+ y5 K5 o0 j& f1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.
$ ^$ ]6 m. }6 U& {. f. \$ {! b5 |6 l5 ~1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping8 w S: f0 s% ]! [4 N
1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report. y( s3 P/ Q3 j7 m
1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro$ n0 E: V1 }" e0 r- Z
1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode- Z$ h3 z# H2 S0 O& V+ U
1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.6 @% l$ v- q1 t" I5 X0 T
1201897 SIP_layout IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.
0 u, r8 ^% R2 s. o3 L6 W1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs
, c' {7 q6 f9 m: y7 F% b8 ?7 W1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017
! W5 Y \# E) m# B; p% K! }; t1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor
* n$ @; L( ^: V! [: n1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout/ ^6 z0 D- o. J! `
1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor" G1 ]/ ]3 O' }7 E; q$ u* A- F6 `
1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct1 {+ w( g# c+ @9 G, ^0 \. \
1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.& l. K- b9 g5 x4 r7 m* v
1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error
: w% B, t; j" f4 S( P3 ]: e1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails
& d. Y+ L7 E3 J5 }, v1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga
* \3 J2 o; L0 E5 s/ k8 d* O1 G9 ]; v1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.; a5 b( ?0 \/ _, j8 Y
1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored. J6 y6 S. j1 x( b
1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor+ F+ o* e+ q3 y6 ]& h
1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.
( h/ }/ O3 J. N5 d3 W( L7 [0 c1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro+ ]% H, f; L$ |, L! j: c
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